1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) having a self-test function, and particularly to an improved DRAM having a self-test function capable of performing a self-test function in the interior of a DRAM chip and reducing a test time of memory cells.
2. Description of the Conventional Art
Referring to FIG. 1, a conventional DRAM 100 having a self-test function includes a row address buffer 16, a row decoder 18, a column address buffer 20, a column decoder 22, a memory cell array 24, and a gate unit 26. In addition, there are further provided an entry/exit control unit 10, a clock generating unit 12, an address counter 14, a data generating unit 28, and a data comparison unit 30.
That is, the conventional DRAM 100 having a self-test function includes the entry/exit control unit 10 for entering a built-in self-test (hereinafter called BIST) mode so as to test a memory cell in accordance with an externally applied row address strobe signal RASB, column address strobe signal CASB, write enable signal WEB, and specific address signals A0 and A1 and for exiting from the BIST mode, the clock generating unit 12 for receiving a row address strobe signal RASB and a column address strobe signal CASB and for generating a predetermined interior clock signal, the row address counter 14 for counting an interior clock signal outputted from the clock generating unit 12 in accordance with a control of the entry/exit control unit 10 and for outputting column address count signals C0-C9, a read/write signal R/W, and a test pattern signal CBO, the row address buffer 16 for receiving row address count signals R0-R9 and a read/write signal R/W outputted from the address counter 14 in accordance with a control of an entry/exit control unit 10 and for buffering externally applied address signals A0-An, the row decoder 18 for decoding an output signal of the row address buffer 16, the column address buffer 20 for receiving column address count signals C0-C9 and a read/write signal R/W outputted from the address counter 14 in accordance with a control of the entry/exit control unit 10 and for buffering externally applied address signals A0-An, the column decoder 22 for decoding an output signal of the column address buffer 20, the memory cell array 24 including a plurality of memory cells which are selected by the column decoder 22 and the row decoder 18, the gate unit 26 having a plurality of gates for controlling an input/output of a data read/write from the memory cell array 24, the data generating unit 28 for outputting a test data having a check board pattern to the memory cell array 24 through the gate unit 26 in accordance with a read/write signal R/W and a test pattern signal CBO outputted from the address counter 14, and the data comparison unit 30 for comparing a test data outputted from the data generating unit 28 with a test data written on the memory cell array 24 and outputted through the gate unit 26 and for outputting an error flag.
As shown in FIG. 2, the address counter 14 includes a row address counter 14A for counting an interior clock signal outputted from the clock generating unit 12 and for generating row address count signals R0-R9, a column address counter 14B for counting a most significant bit (MSB) signal R9 of the row address counter 14A and for generating column address count signals C0-C9, a read/write counter 14C for counting a MSB signal C9 of the column address counter 14B and for generating a read/write signal R/W, and a check board counter 14D for counting a read/write signal R/W outputted from the read/write counter 14C and for generating a test pattern signal CB0.
The operation of the conventional DRAM having a self-test function will now be explained with reference to the accompanying drawings.
To begin with, referring to FIGS. 3A through 3C, a column address strobe signal CASB and a write enable signal WEB are enabled in accordance with a WCBR (WEB & CASB before RASB) mode before a row address strobe signal RASB is enabled.
Here, as shown in FIGS. 3D and 3E, when an address signal A0 of a high level and an address signal A1 of a low level are applied to the DRAM 100, and the DRAM 100 enters the BIST mode, and the entry/exit control unit 10 generates an entry signal.
When the DRAM 100 enters the BIST mode, the DRAM 100 is controlled in the CBR (CASB before RASB) mode. Referring to FIGS. 3C through 3E, when a write enable signal WEB becomes a high level, the address signals A0 and A1 become a "Don't care signals". Referring to FIGS. 3F through 3H, when address signal A0 and A1 become a high level, the write enable signal WEB becomes a Don't care state. During the BIST mode, the data output driver is not in operational.
In addition, the clock generating unit 12 receives a row address strobe signal RASB and a column address strobe signal CASB, and outputs a predetermined interior clock signal to the address counter 14.
The address counter 14 generates a read/write signal R/W, a test pattern signal CBO, row address count signals R0-R9, and column address count signals C0-C9, and the data generating unit 28 writes a test data in a write cycle of a self-test cycle on all cells of the memory cell array 24 in accordance with the row decoder 18 and the column decoder 22.
Thereafter, the data comparison unit 30 reads a test data stored in the memory cell array 24 in a read cycle of a self-test cycle, and detects an error by comparing a read test data with a test data outputted from the data generating unit 28. When an error occurs, the data generating unit 28 outputs an error flag to the outside, and the thusly outputted error flag is maintained until the BIST mode is finished.
In addition, the data generating unit 28 generates a test data having a pattern opposed to the test data. Thereafter, read/write and comparison process are performed.
In a DRAM of 4M and a parallel test of 16 bits, the test data can be written and read in cycles of 256K, and the BIST mode is completed in cycles of 256K.
As shown in FIGS. 3A through 3H, the column address counter 14B is connected to the row address counter 14A which is used in the CBR mode or a hidden refresh mode. So, a self-test is performed in a row fast-scan method, and the read/write counter 14C and the check board counter 14D are sequentially connected to the column address counter 14B.
Meanwhile, as shown in FIGS. 3D through 3H, when address signals A0 and A1 of a low level are outputted to the DRAM 100, the DRAM 100 exits from the BIST mode, and the BIST mode is completed when the entry/exit control unit 10 generates an exit signal.
As shown in FIG. 4, when the DRAM 100 is 4M bits, the check board 200 tests 32M bytes, and an error flag which occurs by each DRAM 100 is outputted to the outside through an output pin Dout of the check board 200.
The conventional DRAM having a self-test function has better features such as an easy maintenance of the system and a start-up function test. However, since a CBR mode is necessary so as to perform a test function, a toggle of row and column address strobe signals is additionally necessary.
In addition, the conventional DRAM having a self-test function has a disadvantages in that since a self-test function is performed by writing the test data on all memory cells of the DRAM and comparing the written test data with a predetermined data, memory cells should be refreshed during a self-test operation. In order to overcome the above-mentioned problems, when the self-test function is performed in the CBR mode of the row fast-scan method, it takes long time compared to the self-test function which is performed in the fast page mode.
Furthermore, since the conventional DRAM having a self-test function does not generate an end flag after the end of the BIST mode, the end of the BIST mode should be recognized from a counter of the external DRAM.